CosaSeminario
Quando5/4/2017 - 10:00
DoveAula Multimediale
ReferenteFederico Fontana
Emailfederico.fontana@uniud.it

KDetSim: A tool to simulate signal in semiconductor detectors

Gregor Kramberger

Jozef Stefan Institute (Slovenia)

A software package for fast simulations of signal in semicon- ductor detectors will be presented. It is a class library which is based on ROOT analysis framework and uses its tools for I/O and visualiza- tion. The tools are complementary to the TCAD tools as they allow Monte-Carlo approach to detector properties studies, which are [...]

CosaSeminario
Quando17/3/2017 - 14:30
DoveSala Riunioni
ReferenteAngelo Montanari
Emailangelo.montanari@uniud.it

Sat-Based Counterexample-Guided Abstraction Refinement

Andrea Brunello

Corso di Temporal Logics: Satisfiability Checking, Model Checking, and Synthesis

CosaSeminario
Quando17/3/2017 - 14:30
DoveSala Riunioni
ReferenteAngelo Montanari
Emailangelo.montanari@uniud.it

Learning Probabilistic Automata for Model Checking

Kevin Roitero

Corso di Temporal Logics: Satisfiability Checking, Model Checking, and Synthesis

CosaSeminario
Quando17/3/2017 - 14:30
DoveSala Riunioni
ReferenteAngelo Montanari
Emailangelo.montanari@uniud.it

Probabilistic Model Checking of Incomplete Models

Andrea Viel

Corso di Temporal Logics: Satisfiability Checking, Model Checking, and Synthesis

CosaTesi di laurea
Quando14/3/2017 - 12:30
DoveSala Riunioni
ReferenteFabio Zanolin
Emailfabio.zanolin@uniud.it

Strategie di ottimizzazione in modelli matematici per la corsa sportiva

Massimiliano Zuliani

Laureando magistrale in Matematica